The CD4050 hex buffers are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. These devices feature logic level conversion using only one supply voltage (VDD). The input signal high level (VIH) can exceed the VDD supply voltage when these devices are used for logic level conversions. These devices are intended for use as hex buffers, CMOS to DTL/ TTL converters, or as CMOS current drivers, and at VDD = 5.0V, they can drive directly two DTL/TTL loads over the full operating temperature range.

• Inverting IC that can convert High logic level to Low level
• High source and Sink Current as it has the capability of driving 2 TTL Loads at 5V over full temperature range.
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1A at 18 V Over Full Package Temperature Range; 100 nA at 18 V and 25C
• 5-V, 10-V, and 15-V Parametric Ratings
• It is available in 16 pin packages of PDIP, SOIC, TSSOP, SO.
• Special input protection to protect inputs against static discharges.

• Wide supply voltage range: 3V to 15V
• Low power: 100 nW (typ.)
• High noise immunity: 0.45 VDD (typ.)
• Separate SET and RESET inputs for each latch
• NOR and NAND configuration
• 3-STATE output with common output enable

• The supply voltage of IC 4017 ranges from 3V to 15V, usually +5V
• This IC is well-matched with Transistor-Transistor Logic or TTL.
• The operational speed/CLK speed of this IC is 5 MHz.
• It provides support to10 outputs that are decoded.
• It is available in different packages like 16-pin GDIP, PDIP & PDSO
• Input high time 30 ns
• Output current is 10 mA
• Noise immunity is high typically 0.45 VDD
• Operation is completely static
• Low power like 10 W
• Speed operation is medium like 5.0 MHz with 10V VDD
• Input Voltage or Vin ranges from 0.5 VDC to VDD +0.5 VDC
• TS or Storage Temperature ranges from 65C to +150C
• VDD or DC Supply Voltage ranges from 0.5 VDC to +18 VDC
• PD or Power Dissipation is Dual-In-Line is 700 mW
• TL or Lead Temperature is 260C

• Asynchronous Set-Reset Capability
• Static Flip-Flop Operation
• Medium-Speed Operation: 16 MHz (Typical) Clock Toggle Rate at 10-V Supply
• Standardized Symmetrical Output Characteristics
• Maximum Input Current Of 1- A at 18 V Over Full Package Temperature Range:
  • 100 nA at 18 V and 25C
• Noise Margin (Over Full Package Temperature Range):
  • 1 V at VDD = 5 V
  • 2 V at VDD = 10 V
  • 2.5 V at VDD = 15 V

• Wide supply voltage range 3.0V to 15V
• Low power 10 nW (typ.)
• High noise immunity 0.45 VDD (typ.)
• Buffered Inputs and Outputs
• Standard Symmetrical Output Characteristics
• 100% Tested for Maximum Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1A at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC

The CD4081 quad gate is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs protected against static discharge with diodes to VDD and VSS.

1. Operating Voltage: 5V, 10V, 15V DC
2. Maximum Input Current: 1uA
3. Hysteresis Voltage Typically 0.9 V at VDD: 5 V and 2.3 V at VDD: 10 V
4. Noise Immunity Greater Than 50%
5. Unlimited input rise and fall times

The 4077 is a quad 2-input EXCLUSIVE-NOR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. The 4077 operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

• Wide range of digital and analog signal levels: digital 3 – 15V, analog to 15Vp-p
• Low “ON” resistance: 80Ω (typ.) over entire 15Vp-p
  • signal-input range for VDD − VEE = 15V
• High “OFF” resistance:
  • channel leakage of ±10 pA (typ.) at VDD − VEE = 10V
• Logic level conversion for digital addressing signals of
  • 3 – 15V (VDD − VSS = 3 – 15V) to switch analog signals
  • to 15 Vp-p (VDD − VEE = 15V)
• Binary address decoding on chip

• High-Voltage Types (20V Rating)
• CD4071BMS Quad 2-Input OR Gate
• CD4072BMS Dual 4-Input OR Gate
• CD4075BMS Triple 3-Input OR Gate
• Medium Speed Operation: tPHL, tPLH = 60ns (typ) at 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Standardized Symmetrical Output Characteristics

• High-Voltage Types (20V Rating)
• CD4073BMS Triple 3-Input AND Gate
• CD4081BMS Quad 2-Input AND Gate
• CD4082BMS Dual 4-Input AND Gate
• Medium Speed Operation: tPLH, tPHL = 60ns (typ) at VDD = 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC

• Input levels: CMOS level
• 16-line demultiplexing capability
• Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs
• Complies with JEDEC standard no. 7 A
• ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200V
• Multiple package options
• Specified from -40C to +85C and -40C to +125C

• Supply voltage ranges from 3v to 18v
• Set-up-time is 150, 70, and 40ns at 5v, 10v, and 15v respectively
• Strobe pulse width is 400, 160, and 100ns at 5v, 10v, and 15v respectively
• Hold time is zero
• 100% tested for quiescent current at 20v
• Having high input current of 1uA (max.) at 18v
• Maximum output current sourcing of 25mA
• Operating temperature ranges from -40 C to 85 C
• Storage temperature ranges from -65 C to 150 C