CD4094 Shift Register

CD4094 Shift Register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the STROBE input is high. Data in the storage register appears at the outputs whenever the OUTPUT-ENABLE signal is high.

Specifications:

• High Voltage Type (20V Rating)
• 3-State Parallel Outputs for Connection to Common Bus
• Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges for Cascading
• Medium Speed Operation – 5MHz at 10V (typ)
• Quiescent Current at 20V
• Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range) – 1V at VDD = 5V – 2V at VDD = 10V – 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings

Datasheet:

CD4094 IC Datasheet